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November 05, 2009

Avago Technologies Provides Critical IP to Juniper for Development of High-Performance Silicon


Avago Technologies has announced that it provided critical IP to Juniper Networks to enable the development of the company’s high-performance silicon devices.


From devices to data centers, from consumers to the cloud, Juniper delivers innovative software, silicon and systems that transform the experience and economics of networking. The new Juniper designs are part of the Junos Trio chipset that enables the delivery of Juniper’s MX-3D platforms.

“Avago’s multi-gigabit SerDes cores meet our stringent performance requirements,” said R.K. Anand, executive vice president of Foundation Technologies at Juniper Networks (News - Alert), in a release.
 
He added that the cutting edge IP from Avago for SerDes and high-speed I/O are essential technologies that enable the company to deliver “compelling” and innovative solutions in silicon for the customers.
 
Featuring close to100 SerDes channels, each device is capable of driving a lossy backplane channel and multiple backplane connectors. Avago said that its decision feedback equalization (DFE) and modular architectures enable high-density, low-power solutions, which are critical in today’s demanding applications.
 
Frank Ostojic, vice president and general manager for ASIC Products Division at Avago, said that Juniper has chosen Avago and has engaged it closely on such “breakthrough” projects.
 
“This will enable us to showcase our embedded SerDes leadership within the industry and meet Juniper’s needs of unprecedented performance and scale for their new product,” he said.
 
Avago is a supplier of analog interface components for communications, industrial, and consumer applications. The company leverages its core competencies in III-V compound and silicon semiconductor design and processing to provides an extensive range of analog, mixed signal and optoelectronics components and subsystems.

Earlier this month, the company announced expansion of its family of SFP+ optical transceiver modules for next-generation 10 Gbps Ethernet equipment designs.

Anshu Shrivastava is a contributing editor for TMCnet. To read more of Anshu’s articles, please visit her columnist page.

Edited by Patrick Barnard

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